EDA News eI Monday January 26, 2004 From: EDACafe ÿÿ Previous Issues _____ http://www.mentor.com/fpga _____ About This Issue eI Bits & Bytes ... and the plucky Spirit rover has started calling home again _____ January 19 - 23, 2004 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ 1 - Counting angels on the head of a pin Infineon Technologies has announced the availability of a new generation of highly integrated SoC devices, manufactured using the company's 0.13-micron process. The newly released SoCs integrate a 1.6 Gigabit-per-second (Gbit/s) read channel core, a 3 Gbit/s Native Serial ATA interface, a 16-bit microcontroller, a hard disk controller, embedded memory, and a quality monitoring system. You're way too jaded if you can't just step back for a minute and think about the level of on-chip integration that's being achieved here. 2 - When you're smiling, when you're smiling, the whole world smiles with you Per the Press Release: "North American-based manufacturers of semiconductor equipment posted $1.1 billion in orders in December 2003 (three-month average basis) and a book-to-bill ratio of 1.20, according to the December 2003 Express Report published today by SEMI. A book-to-bill of 1.20 means that $120 worth of new orders were received for every $100 of product billed for the month. The three-month average of worldwide bookings in December 2003 was $1.1 billion. The bookings figure is 19 percent above the revised November 2003 level of $923 million and 33 percent above the $827 million in orders posted in December 2002." Stanley Myers, President and CEO of SEMI, is quoted in the Press Release: "The December data support the positive outlook for strong growth in semiconductor capital investment this year. Analysts presenting at the SEMI Industry Strategy Symposium this month were in agreement that 2004 is shaping up to be a double-digit growth year for the global semiconductor equipment industry." 3 - No time like the present to re-visit that lease Meanwhile, although the revenue numbers in the semiconductor industry may be up, the vacancy rate in Silicon Valley inches down only oh-so-slowly. Per Roger Oser, Executive Vice President at Predium Real Estate Services (San Jose, CA) the current vacancy rate in Silicon Valley is running at approximately 1 empty building for every 2 that are occupied. (What's normal in a healthy economy? A 5-to-7 percent vacancy rate, according to Oser.) So, I'm guessing that it's still pretty much a renter's market in Silicon Valley when it comes to negotiating your next lease. If you haven't relocated in the last 3 years to bring your costs-per-square-foot down to post-boom reality, there's no time like the present. 4 - Jan Rabaey and DesignCon 2004 When I spoke by phone on Friday, January 16th, with Dr. Jan Rabaey, EECS Professor at U.C. Berkeley and Director of the Gigascale Silicon Research Center, he was in a hurry. He had meetings to attend, classes to prepare for the upcoming semester, and was leaving the very next day for a 4-day trip to Germany where he was also presenting a class. For those of you who don't know Rabaey, he's also scientific co-director of the Berkeley Wireless Research Center, has been a visiting professor at the University of Pavia, Italy, and Waseda University, Japan, has authored or co-authored numerous papers and books in the area of signal processing, digital architectures and circuits, and design automation - and is the author of what is described as a "popular textbook," Digital Integrated Circuits - A Design Perspective. ("Popular" is a relative term here, however. It's probably not too "popular" on the night before a big EE final based on the text.) In any case, Rabaey took the time to outline for me the keynote address he'll be delivering at the outset of DesignCon on February 2nd, at the Santa Clara Convention Center. Here's what he told me: "I'll be giving a talk that is titled, 'Design in the Late Silicon Era.' What I'll really be addressing is some of the big issues that we'll be seeing in the next decade from a design perspective - in particular, as we move to the end of the existing silicon roadmap and beyond. There's a key or lead theme in the talk, which is the move to platform-based and software-based solutions as a result of the business shifts that are happening today. [The trend] is pretty noticeable across a wide variety of industries, as we see more programming [in products]. The consumer, multimedia, and automotive industries are among the many that are shifting in that paradigm - and perhaps the move to structured ASICs is impacting things as well. All of this means there will be a shift away from the needs from a design automation perspective towards an application perspective." "Following those comments, I'll speak about the three challenges we're facing in the future. The first are real showstoppers - power and energy. If we don't do something drastic and soon, these things are going to [inhibit] the roadmap for integration. We need to go more aggressively towards voltage scaling, which is the only fundamental way of dealing with power and energy problems if we want to keep making progress." "The second challenge is variance on new devices. Thresholds are becoming dominant, predictability is getting harder and harder, and therefore timing analysis must be done differently. There must be dynamics on-chip to adjust for adaptive timing." "The third challenge is reliability - timing uncertainties, software errors, scaled supply voltages. Many things will contribute to errors, which presents a very scary perspective. There's no way to catch all of those things in advance; therefore, chips that can deal with their own errors will be absolutely critical. It challenges the traditions of Boolean logic that we've been building on for the last 30 years or longer, but errors are going to be quite crucial going down the road. I'll talk about all of this and show some examples. However, I only have 20 minutes for the talk and it's taken me 5 minutes just to say this much." "I'm optimistic about the future, nonetheless. There are people who are working on these problems. We've got the Gigascale Research Center at U.C., which has all of the top-notch researchers [addressing these things]. Some good solutions to all of this are bound to come out of that." If you can be in Santa Clara on the 4th, it will be well worth your time to hear Rabaey speak. His energy and knowledge are quite compelling. 5 - Speaking of keynotes As many of you are well aware, Penny Herscher is no longer at Cadence Design Systems. Her departure has been a quiet one and the reigns of the Design and Verification Division of the company have been handed over to the new Executive Vice President and General Manager, the very accomplished Ping Chao. Herscher had been slated to deliver the keynote address at DVCon on March 2nd. In light of recent developments, DVCon organizers have now announced that Cadence President and CEO Ray Bingham will be delivering the talk instead. On a personal note, I would extend best wishes to Herscher on her next endeavor. Someone who's known Herscher for a long time said to me recently, "Penny's not just charismatic, she's a force of nature!" Industry News - Tools and IP Cadence Design Systems, Inc. announced it will release "key products" of the Cadence Encounter design platform on the AMD64 processor-based systems running 64-bit Linux. The company says the move will "offer customers increased capacity and high performance for implementing complex SoC designs." Ben Williams, Director, Server/Workstation Business Segment in AMD's Microprocessor Business Unit, is quoted in the Press Release: "Cadence solutions ported to AMD Opteron processor-based systems help address the increasing design computing capacity and performance needs of our joint customers." Also from Cadence - The company announced it has released key products of the Cadence Encounter design platform on Intel Itanium 2-based systems running the 64-bit Linux operating system. Cadence says it has ported the products to Intel Itanium 2-based Linux platforms to "offer customers increased capacity and higher performance critical for designing the largest and most complex SoC designs in the industry today." Guru Bhatia, Director of IT Engineering Computing at Intel, is quoted: "We are excited to see the release of Cadence products on Intel Itanium 2-based systems offering the 64-bit computing to meet ever increasing design computing capacity and performance needs. Coupled with the Cadence suite of semiconductor design and verification tools, the Itanium 2-based platform provides the technical advantage to design complex silicon products for the EDA engineering community." Open Core Protocol International Partnership (OCP-IP) announced the availability of OCP 2.0 compliant transactional models implemented in SystemC. Per the Press Release: "The models standardize the way OCP- based communication is modeled at various abstraction levels, and their availability ensures increased model interoperability and reusability. Work on the project was spearheaded by Nokia, in collaboration with Prosilog, Sonics Inc., and Synopsys. The models provide an OCP point-to-point channel model for SystemC, which can be used to connect SystemC behavioral models with each other, as well as to complex interconnect models. The latest version of the OCP 2.0 compliant SystemC transaction model library now contains an easy-to-use OCP API." TriCN announced the immediate availability of its Base I/O library for flip-chip and bond-wire applications in the TSMC 90-nanometer process. The company describes the library as "a comprehensive set of cells containing all elements necessary for pad ring assembly. TriCN's Base I/O library is particularly well suited to the demands of high-performance interface applications. The cells are designed to accommodate more robust power and ground demands, allowing for an effective area gain compared to competing libraries. All cells feature built-in noise isolation to provide improved operation and reliability in high-performance applications. Additionally, the library is designed to support not only bond-wire, but also flip-chip packaging typically found in high-speed ICs." I had a chance to talk briefly about the announcement by phone with Steve McConnell, Vice President of Marketing, and Ron Nikel, Co-Founder and CTO for TriCN. They were sitting in a conference room in San Francisco, CA. Steve: We're one of only two semiconductor companies actually located in San Francisco. We're one block from the ballpark [PacBell] in a converted warehouse. It's not a typical setting, but about half of our staff lives in San Francisco and our location is close to the freeway, [so it works for us]. TriCN designs IP. Right now, most of [our work] is at .13 micron, although we're also supporting some .18-micron IP. We're not doing customized work there, however, as all of those products are stable and ready to be delivered. The new thing is 90 nanometers. It's not currently the vast majority of our work, but we have secured some customer wins at 90 nanometers, which have resulted in tape-outs. Ron: We have a roadmap underway at 65 nanometers. We'll probably be starting to see 65 nanometers in 2005. We have actually done some work at 65 nanometers, but those are very advanced products with a large customer." Steve: "This is the evolution - people pushing bandwidth will look to 90 nanometers, especially in graphics and memory and networking. At a high level, what differentiates our Base I/O library is that, while it's broadly applicable for any application, it's specifically designed for high-performance applications. Our niche is the high-performance interface - we're specialists there. The free libraries that are available require too much re-engineering, so we have developed our own." True Circuits, Inc. announced that Parama Networks Inc. has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-chip (add-drop multiplexers), fabricated in UMC's 130-nanometer process technology. The companies say this chip offers system designers, for the first time on a single piece of silicon, all of the functions necessary to build ADMs and other next generation network equipment. Kent Goodin, Vice President for VLSI Engineering at Parama Networks, is quoted in the Press Release: "The True Circuits 1.2GHz clock generator PLL is the core component that allows the multi-rate SONET/SDH ports on the ADM-on-a-Chip to operate within the required industry jitter specifications across all supported rates." Virtual Silicon, Inc. announced the introduction of the VIP PowerSaver standard cell library, which the company says is the first library supporting the creation of power islands available from a commercial IP company. The VIP PowerSaver standard cells are targeted for the TSMC 130-nanometer process characterized for 0.8, 1.0, and 1.2 volt operation. Per the Press Release: "SoC designs, using power islands to dynamically control the voltage and frequency of the islands, can see up to a 50 percent reduction in power consumption, resulting in longer operating battery life for mobile electronics." John Cornish, Director of Product Marketing at ARM, is also quoted: "Having already hardened several different ARM cores and other IP blocks using Virtual Silicon standard cells, ARM has first-hand knowledge of Virtual Silicon's capability. Virtual Silicon's Power Island-enabling IP is a key element in the proliferation of the ARM Intelligent Energy Manager (IEM) technology." Also from Virtual Silicon - The company, in conjunction with MoSys, Inc., announced the formation of a partnership to collectively offer a "comprehensive low power IP solution" for TSMC's 130-nanometer processes. Virtual Silicon says it will contribute VIP PowerSaver standard cells, interface IP (basic I/O, application specific I/O and PLL) and power management IP. MoSys says it will add its new low-power, single-port and dual-port 6T-SRAM-R compiled memories as well as MoSys' high-density, low-power 1T-SRAM-M memory technology. Per Barry Hoberman, President and CEO of Virtual Silicon: "Virtual Silicon's strategic focus is to enable SoC designers to solve the crisis of power at 130 and 90 nanometers. Teaming up with MoSys on this mission for memory means the customer is getting an integrated solution from the best in class IP providers." Per Fu-Chieh Hsu, President and CEO of MoSys: "MoSys is addressing the requirements of SoC designers to reduce power consumption in the latest generation processes while minimizing chip cost with our innovative 1T-SRAM-M and 6T-SRAM-R memory technologies. We are pleased to partner with Virtual Silicon to offer customers a complete power-optimized foundation IP solution." Coming soon to a theater near you Intel Developer Forum (IDF) - This is a well-attended event (not just hundreds, but thousands of interested individuals) unfolding February 17th to the 19th at Moscone Center in San Francisco, CA. There are two parts to the event: The Systems Conference - "An unparalleled opportunity to evaluate new products and understand how upcoming technologies will impact your computing and communication products : you'll gain a better understanding of where platform technologies are heading and what new opportunities will emerge as a result" - and the Solutions Conference - "Provides a unique opportunity for representatives from across the enterprise ecosystem to discuss recommendations and issues for deploying mobility in the infrastructure. This impactful, two-day conference will bring together IT managers, service/solution providers, and ISV applications and tools vendors." That "impactful" bit is, in itself, enough of a reason to attend IDF. Better register now. ( www.intel.com/idf/us/spr2004/index.htm ) Distinguished Speaker Series - This particular series is taking place in Palo Alto, CA, for those of you living in Silicon Valley. Coming up on February 19th, for instance, Gordon Bell and Jim Gemmell from the Microsoft Media Presence Research Group will discourse on the MyLifeBits project, which is putting all of Bell's personal documents and media in a PC for both daily and archival applications. Minimally, those suffering from paper clutter will want to attend that talk. The speaker series is a co-production of the Software Development Forum, the Computer History Museum, ACM, and the Chinese Software Professionals Association. ( ) Newsmakers Circuit Semantics, Inc. (CSI) and Legend Design Technology, Inc. announced that the companies have signed an OEM agreement. Under the terms of the agreement CSI has integrated Legend's MSIM circuit simulator with CSI's DynaCell and DynaCore circuit characterization software products. Per the Press Release: "With MSIM, CSI can now provide customers with a complete circuit characterization flow that includes simulation and RC reduction, as well as circuit characterization and timing sign-off." Ewald Detjens, Circuit Semantics' CEO, is quoted: "As a result of the synergy between our companies and our customers' requests, we worked quickly to successfully integrate Legend's MSIM circuit simulator with our characterization products." You-Pang Wei, Legend's CEO, is also quoted: "We are optimistic that our partnership will add value to our mutual customers design flows." SynTest Technologies, Inc. announced that the company has opened a new center in Shanghai, for R&D and customer support. L.T. Wang, SynTest President and CEO, is quoted in the Press Release: "The growing interest in our DFT [design-for-test] products and services, and the continuing development as well as enhancement of our products requires that we continue to add to our R&D staff. China, with its rapidly expanding IC design market and fabless design houses, has become an important market for us. We have appointed Hyperform Technologies Co., Ltd. as our distributor for China. Hyperform - led by James Liu, ex-Director of Sales at Cadence China, a successful and seasoned professional in the field of electronic design and EDA - was a logical choice for us." Tera Systems, Inc. announced the appointment of Gregg Westerbeck as Vice President of Sales. He will report to Alain Labat, President and CEO. Westerbeck has more than 20 years of experience in the high-tech sector. Prior to joining Tera, Westerbeck was as Vice President at both Mercury Interactive/Kintana and Manugistics. Previously he was at Cadence Design Systems for 6 years, and before that served in various capacities at Parametric Technology, Micro Component Technology, Teradyne, and Ingersoll-Rand. In the category of ... Flu, flu everywhere We've been doing our share of contributing to the CDC's statistics on flu this past week. Hope your family has been spared. As a result, this newsletter's a bit shorter than normal, but on the theory that "something's better than nothing" and that "this too shall pass," I'm submitting an abbreviated newsletter to the edatoolscafe.com Web Master, the ever patient Adam Heller. He kindly offered to give me more time, but I need to go rest and take plenty of fluids. Talk to you all next week. --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are registered as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your newsletter's details, including format and frequency, or to discontinue this service, please navigate to . If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . 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